1. Technical Field
Embodiments of the present disclosure relate generally to programming semiconductor memory devices. In particular, the present disclosure is concerned with a programming method for shortening a program time, and a semiconductor memory device therefor.
2. Related Art
Among semiconductor memory devices, nonvolatile memory devices are operable to store data and maintain the stored data therein even without a power supply. Increasingly used in portable memory apparatuses in recent years, nonvolatile memory devices are required to be lighter weight and to have larger data storage capacities.
Nonvolatile memory devices may operate in two states of threshold voltages where the two states respectively correspond to erased and programmed states. More particularly, memory cells within the nonvolatile memory device may be classified as being either erased, or in a programmed state, by the threshold voltages present in the memory cell. That is, the erased and programmed states may correspond to one of the two threshold voltages which further correspond to a logical “on” and “off” which may also be referred to as a logical “1” or “0,” or vice versa depending on the specific device implementation A nonvolatile memory device memory cell operating in this manner is called a “single level cell” (SLC). However, multi-level or multi-bit nonvolatile memory devices have been proposed to meet the need for larger data storage capacity devices. In a multi-bit nonvolatile memory device, threshold voltages of memory cells are grouped in plural states, that is, more than two. A memory cell of a multi-bit nonvolatile memory device is therefore called a “multi-level cell” (MLC). An exemplary procedure of programming an MLC is as follows.
FIG. 1 graphically shows program voltage variations over time by a general programming operation.
A case of an MLC having three or more threshold voltage states will be described as an example. For instance, memory cells operating with four threshold voltage distributions may be conditioned in an erased state, a first programmed state, a second programmed state and a third programmed state. A programming operation referred to as an incremental step pulse programming (ISPP) mode is conducted by gradually increasing a program voltage by a predetermined rate of step pulse, which is useful to restrain extensions of threshold voltage distributions.
However, the ISPP programming operation takes a long program time to condition memory cells into the first through third programmed states. The program time is long because the memory cells are processed in sequence from the first programmed state to the third programmed state. Further contributing to the length of programming time required, each program stage for each programmed state requires a verifying step that applys a program-verify voltage Vf, subsequent to a program voltage Vpgm, to a selected word line. The program time therefore becomes longer in relation to the number of MLC bits. For example, in reference to FIG. 1, in the time segment where the first, second and third program periods (1st, 2nd and 3rd PGM periods) overlap with each other, the third program-verify voltage Vf is sequentially applied to all of the memory cells. Thus, the verification increases the program time by the number of the MLC bits.